1. Field of the Invention
The present invention relates generally to semiconductor memory devices for a simple cache system, and more particularly, to semiconductor memory devices having a cache memory integrated on a chip on which the semiconductor memory device is formed.
2. Description of the Prior Art
Conventionally, in order to improve cost performance of a computer system, a small capacity and high-speed memory has been frequently provided as a high-speed buffer between a main memory structured by a low-speed but large capacity and low-cost dynamic random access memory (DRAM) and a central processing unit (CPU). The high-speed buffer is referred to as a cache memory. A block of data which the CPU may request is copied from the main memory and stored in the high-speed buffer. The state in which data stored in an address, in the DRAM, which the CPU attempts to access exist in the cache memory is referred to as "hit". In this case, the CPU makes access to the high-speed cache memory, and acquires the requested data from the cache memory. On the other hand, the state in which data stored in an address which the CPU attempts to access does not exist in the cache memory is referred to as "cache miss". In this case, the CPU makes access to the low-speed main memory, acquires the requested data from the main memory and at the same time, transfers to the cache memory a data block to which the data belongs.
However, such a cache memory system could not be employed in a small-sized computer system attaching important to the cost because it requires a high-cost and a high-speed memory. Conventionally, a simple cache system has been configured utilizing a high-speed access function of a general-purpose DRAM, such as a page mode and a static column mode.
FIG. 1 is a block diagram showing a basic structure of a conventional DRAM device having a function of a page mode or a static column mode.
In FIG. 1, a memory cell array 1 has a plurality of word lines and a plurality of bit line pairs arranged intersecting with each other, memory cells being provided at intersections thereof, respectively. In FIG. 1, there are typically shown only a single word line WL, a single bit line pair BL and BL and a single memory cell MC provided at an intersection of the word line WL and the bit line BL. The word lines in the memory cell array 1 are connected to a row decoder portion 3 through a word driver 2. In addition, the bit line pairs in the memory cell array 1 are connected to a column decoder portion 6 through a sense amplifier portion 4 and an I/O switching portion 5. A row address buffer 7 is connected to the row decoder portion 3, and a column address buffer 8 is connected to the column decoder portion 6. A multiplex address signal MPXA obtained by multiplexing a row address signal RA and a column address signal CA is applied to the row address buffer 7 and the column address buffer 8. An output buffer 9 and an input buffer 10 are connected to the I/O switching portion 5.
FIGS. 2A, 2B and 2C are waveform diagrams showing operations in an ordinary read cycle, a page mode cycle and a static column mode cycle of the DRAM, respectively.
In the ordinary read cycle shown in FIG. 2A, the row address buffer 7 first acquires the multiplex address signal MPXA at the falling edge of a row address strobe signal RAS and applies the same to the row decoder portion 3 as a row address signal RA. The row decoder portion 3 is responsive to the row address signal RA for selecting one of the plurality of word lines. The selected word line is activated by the word driver 2. Consequently, information stored in the plurality of memory cells connected to the selected word lines are read out onto the corresponding bit lines, respectively. The information are detected and amplified by the sense amplifier portion 4. At this time point, information stored in the memory cells corresponding to one row are latched in the sense amplifier portion 4. Then, the column address buffer 8 acquires the multiplex address signal MPXA at the falling edge of a column address strobe signal CAS and applies the same to the column decoder portion 6 as a column address signal CA. The column decoder portion 6 is responsive to the column address signal CA for selecting one of information corresponding to one row latched in the sense amplifier portion 4. This selected information is extracted to the exterior through the I/O switching portion 5 and the output buffer 9 as output data D.sub.OUT. An access time (RAS access time) t.sub.RAC in this case is the time period elapsed from the falling edge of the row address strobe signal RAS until the output data D.sub.OUT becomes valid. In addition, a cycle time t.sub.c in this case is the sum of the time period during which the device is in an active state and an RAS precharge time t.sub.RP. As a standard value, t.sub.c is approximately 200 ns when t.sub.RAC is 100 ns.
In the page mode cycle and the static column mode cycle shown in FIGS. 2B and 2C, memory cells on the same row address are accessed by changing the column address signal CA. In the page mode cycle, the column address signal CA is latched at the falling edge of the column address strobe signal CAS. Thus, the access time is a time period t.sub.CAC (CAS access time) elapsed from the falling edge of the column address strobe signal CAS until the output data D.sub.OUT becomes valid, which becomes a time period of approximately one-half of the access time t.sub.RAC in the ordinary cycle, i.e., approximately 50 ns, where t.sub.CP denotes a precharge time of the column address strobe signal CAS, and t.sub.PC denotes a cycle time.
In the static column mode, access is made in response to only the change in the column address signal CA, as in a static RAM (SRAM). Thus, the access time is a time period t.sub.AA (address access time) from the time when the column address signal CA is changed to the time when the output data D.sub.OUT becomes valid, which becomes approximately one-half of the access time t.sub.RAC in the ordinary cycle similarly to t.sub.CAC, i.e., generally about 50 ns.
More specifically, in the page mode cycle, when the falling edge of the column address strobe signal CAS is inputted to the column address buffer 8, the column address signal CA is sent to the column decoder. Therefore, any of the data corresponding to one row latched in the sense amplifier portion 4 is made valid, so that the output data D.sub.OUT is obtained through the output buffer 9. Also in the static column mode cycle, the same operation as that in the page mode cycle is performed except a reading operation is initiated in response to the change in address signal.
FIG. 3 is a block diagram showing a structure of a simple cache system utilizing the page mode or the static column mode of the DRAM device shown in FIG. 1. In addition, FIG. 4 is a waveform diagram showing an operation of the simple cache system shown in FIG. 3.
In FIG. 3, a main memory 20 comprises 1M byte which comprises 8 DRAM devices 21 each having 1M.times.1 organization. In this case, the row address signal RA and the column address signal CA having a total of 20 bits (2.sup.20 =1048576=1M) are required. An address multiplexer 22, which applies 10-bit row address signal RA and the 10-bit column address signal CA to the main memory 20 two times, has 20 address lines A.sub.0 to A.sub.19 receiving a 20-bit address signal and 10 address lines A.sub.0 to A.sub.9 applying a 10-bit address signal as multiplexed (multiplex address signal MPXA) to the DRAM devices 21.
It is assumed here that data corresponding to one row selected by a row address RAL has been already latched in the sense amplifier portion 4 in each of the DRAM devices 21. An address generator 23 generates a 20-bit address signal corresponding to data which the CPU requests. The latch TAG) 25 holds the row address RAL corresponding to data selected in the preceding cycle. A comparator 26 compares the 10-bit row address RA out of the 20-bit address signal with the row address RAL held in the TAG 25. When both coincide with each other, which means that the same row as that accessed in the preceding cycle is accessed ("hit"), the comparator 26 generates an "H" level cache hit signal CH. A state machine 27 is responsive to the cache hit signal CH for performing page mode control in which a column address strobe signal CAS is toggled (raised and then, lowered) with a row address strobe signal RAS being kept at a low level. In response thereto, the address multiplexer 22 applies the column address signal CA to the DRAM devices 21 (see FIG. 4). Thus, data corresponding to the column address signal CA is extracted from a group of data latched in the sense amplifier portion in each of the DRAM devices 21. In the case of such "hit", output data is obtained from the DRAM devices 21 at high speed in an access time t.sub.CAC.
On the other hand, when the row address signal RA generated from the address generator 23 and the row address RAL held in the TAG 25 do not coincide with each other, which means that a different row from the row accessed in the preceding cycle is accessed ("cache miss"), the comparator 26 does not generate the "H" level cache hit signal CH. In this case, the state machine 27 performs ordinary RAS and CAS control in the ordinary read cycle, and the address multiplexer 22 sequentially applies the row address signal RA and the column address signal CA to the DRAM devices 21 (see FIG. 4). In the case of such "cache miss", the ordinary read cycle beginning with precharging of the row address strobe signal RAS occurs, so that output data is obtained at low speed in the access time t.sub.RAC. Therefore, the state machine 27 generates a wait signal Wait, to bring a CPU 24 into a Wait state. In the case of "cache miss", a new row address signal RA is held in the TAG 25.
As described in the foregoing, in the simple cache system shown in FIG. 3, data corresponding to one row of the memory cell array in each of the DRAM devices (1024 bits in the case of a 1M bit device) is latched in a sense amplifier portion as one block. Therefore, the block size is unnecessarily large and the blocks (entries) held in the TAG 25 are insufficient in number. For example, in the system shown in FIG. 3, the number of entries becomes 1. Thus, only when access is continuously made to the same row address, cache hit occurs. Consequently, for example, when a program routine bridged over continuous two row addresses is repeatedly implemented, cache miss necessarily occurs, so that a cache hit rate is low.
Meanwhile, as another conventionally example, a simple cache system has been proposed, which is disclosed in U.S. Pat. No. 4,577,293. In this simple cache system, a register holding data corresponding to one row is provided outside a memory cell array. In the case of "hit", the data is directly extracted from this register, so that accessing is speeded up. However, in the simple cache system disclosed in the U.S. Patent, the external register holds data corresponding to one row in the memory cell array, so that the block size is unnecessarily large and the cache hit rate is low as in the conventional example shown in FIG. 1 and 3.